1. Field
The present invention relates to cleaning of unwanted materials deposited on a substrate or other workpiece. Specifically, the invention relates to dissolving deposited metals from the backside and/or edge of a substrate following a deposition.
2. Background
Sub-quarter micron multi-level metallization is one of the key technologies for the next generation of ultra large scale integration (ULSI). The multilevel interconnects that lie at the heart of this technology require planarization of interconnect features formed in high aspect ratio apertures, including contacts, vias, lines and other features. Reliable formation of these interconnect features is very important to the success of ULSI and to the continued effort to increase circuit density and quality on individual substrates and die.
As circuit densities increase, the widths of vias, contacts and other features, as well as the dielectric materials between them, decrease to less than 0.25 .mu.m, whereas the thickness of the dielectric layers remains substantially constant, with the result that the aspect ratios for the features, i.e., their height divided by width, increases. Many traditional deposition processes have difficulty filling structures where the aspect ratio exceeds 4:1, and particularly where it approaches 10:1. Additionally, as the feature widths decrease, the device current remains constant or increases, which results in an increased current density in the feature.
Aluminum and its alloys have been the traditional metals used to form lines and plugs and other features in semiconductor processing. However, with the increase in circuit densities, copper is becoming a choice metal for filling sub 0.25 .mu.m, high aspect ratio interconnect features on semiconductor substrates. Copper and its alloys have lower resistivities compared to aluminum and high electromigration resistance. These characteristics are important for supporting the higher current densities experienced at high levels of integration and increased device speed. Copper also has good thermal conductivity and is available in a highly pure state.
Despite the desirability of using copper for semiconductor device fabrication, choices of fabrication methods for depositing copper into very high aspect ratio features, such as a 10:1 aspect ratio, 0.25 .mu.m wide vias are limited. Precursors for CVD deposition of copper are being developed, and physical vapor deposition into such small features has produced unsatisfactory results because of voids formed in the features. As a result of these process limitations, electroplating, which had previously been used primarily in circuit board fabrication in the electronics industry, is being used to fill features, such as vias, on semiconductor devices. Thus, efforts are being explored to improve the electroplating process to be suitable for substrate manufacturing, especially in high aspect ratio features of substrates.
FIG. 1 is a partial cross section representing a substrate edge with a series of layers deposited thereon. The substrate 2 has a silicon base 4 with an edge profile 6 that typically is beveled with a first bevel 8 on a front side 12 and a second bevel 10 on a backside 14. The base has doped regions 15 that connect to feature 20, such as the contact shown, to form a portion of the circuitry of the semiconductor. A dielectric layer 16 is deposited on the base 4 and is etched to form apertures, followed by the deposition of a barrier layer 18, using Ti, TiN, Ta, TaN, and other known materials. The barrier layer reduces migration and diffusion of adjacent layers and may also provide good adhesion to the silicon oxide and subsequent metal layer. A conductive layer 21, typically aluminum or copper, is deposited over the barrier layer, such as by electroplating, and fills the apertures to form the interconnects between the layers.
The integrity of the barrier layer in the edge region is sometimes compromised in that typical processes such as physical vapor deposition (PVD) and chemical vapor deposition (CVD) may not uniformly deposit around the edge profile. Thus, the conductive layer material may diffuse into the underlying layers and poison the semiconductor device. Furthermore, some backside deposit 22 may occur on the second surface 14, further heightening the possibility of unwanted diffusion into the layers. Because copper has a high diffusion capability and can poison the device, this unwanted deposition can adversely affect the performance gains achieved using copper. Therefore, a preferred substrate fabrication process would remove this copper or other unwanted materials from the backside or from other surfaces where it may have been deposited.
FIG. 2 is a partial cross section representing a desired deposition profile on the substrate 2. The layers are distanced from the edge of the substrate to form an edge exclusion zone 6a. In PVD and CVD processing which are typically dry processes, the ability to define the edge exclusion zone is well known, using for instance, clamp rings, shadow rings, and purge gases. However, electroplating is typically a wet process on a substrate facing downward and is more difficult to control, leading to backside and edge deposits on the substrate. If, for instance, the layers had been deposited as in FIG. 1, then it would be advantageous to remove the layers from the edge to allow the edge exclusion zone. The edge exclusion zone 6a may be from about 1 mm to about 3 mm or more. In processing, there would be less likelihood of the edge deposits being dislocated from the substrate, thereby contaminating subsequent substrates, and less likelihood of unwanted diffusion through the layers.
An advantageous process to reduce or eliminate the unwanted deposition would preferably combine with an existing stage in the electroplating process. Part of the electroplating process involves rinsing the substrate after depositing the material, where the substrate is typically taken to a spin-rinse-dry chamber, represented in FIG. 3. A spin-rinse-dry chamber 23 includes a cover 23a which helps retain the fluids in the chamber. The chamber also includes a chamber top 23b, to which the cover 23a attaches, and a chamber bottom 23c. In one commercial system, the chamber top and bottom separate with a chamber lift 25 to allow a robot (not shown) to insert a substrate 2 into the chamber onto the pedestal 26. The pedestal 26 may have a vacuum port 26a in each pedestal arm 26b that are ultimately connected to a vacuum source 28, where the pedestal arms hold and center the substrate 2 to the pedestal. The pedestal or portion thereof may raise and lower to contact the substrate delivered by the robot. The pedestal 26 supports the substrate 2 during processing. The pedestal actuator 27 rotates the pedestal to spin the substrate to assist in rinsing and/or drying. The chamber top 23b generally includes a plurality of spray nozzles 29. These nozzles spray the rinsing fluid to impact and rinse the substrate surface. Typical rinsing fluids are deionized water, alcohol, or a combination thereof. After rinsing, the pedestal continues to spin the substrate, perhaps at a different speed, to effectively dry the surface.
Therefore, there remains a need for an apparatus and method to remove unwanted backside and edge depositions on a substrate, preferably by integrating the removal process into a spin-rinse-dry chamber.